################################################# ### SET DESIGN VARIABLES ### ################################################# set DesignName "mipsfpga" set FamilyName "ARTIX7" set DeviceName "XC7A200T" set PackageName "SBG484" set SpeedGrade "-1" set TopModule "mipsfpga_nexysvideo" set PartName "XC7A200TSBG484-1" set DcpFile "" set InputMode "EDIF" set Flow "Standard";#Flow can be set to "Incremental" or "Standard" set StrategyMode "default"; #StrategyMode can be set to "timing_qor","fast_turn_around" or "default" #Only one StrategyMode can be specified at a time ################################################# ### ENABLE BETA LICENSE ### ## Beta feature ## ################################################# if {${DeviceName} == "XCVU440"} {enable_beta_device}
################################################# ### SETUP STRATEGY AND FLAGS ### ################################################# puts"StrategyMode is ${StrategyMode}" switch -- $StrategyMode { "timing_qor" { set opt_design_flags "-directive Explore" set place_design_flags "-directive Explore" set route_design_flags "-directive Explore" } "fast_turn_around" { set opt_design_flags "-directive RuntimeOptimized" set place_design_flags "-directive RuntimeOptimized" set route_design_flags "-directive RuntimeOptimized" } default { set opt_design_flags "" set place_design_flags "" set route_design_flags "" } } set write_bitstream_enable "1" ################################################# ### SETUP DESIGN ### ################################################# set_property target_part ${PartName} [current_fileset -constrset] set_property design_mode GateLvl [current_fileset] reset_property SEVERITY [get_drc_checks REQP-46]
### Turn off a restriction on the number of clock objects allowed in a list for create_*clock commands catch {set_param sta.maxSourcesPerClock -1}
### Suppresses warning about multiple objects in a clock list catch {set_msg_config -id {Constraints 18-633} -suppress}
### Demotes error to warning about GTGREFCLK_ACTIVE inserted for multiview instrumentation catch {set_property SEVERITY {warning} [get_drc_checks REQP-46]} catch {set_property SEVERITY {warning} [get_drc_checks REQP-56]}
### Promotes critical warning on unroutability to an error catch {set_msg_config -id {Route 35-162} -new_severity ERROR}
if {${InputMode} == "EDIF"} { set_property edif_top_file ${DesignName}.edf [current_fileset] if {[file exists ${DesignName}.edf]} { read_edif ${DesignName}.edf } if {[file exists ${DesignName}_edif.xdc]} { read_xdc ${DesignName}_edif.xdc } if {[file exists ${DesignName}_floorplan.xdc]} { read_xdc ${DesignName}_floorplan.xdc } set TopModule [find_top] }
if {${InputMode} == "VM"} { if {[file exists ${DesignName}.vm]} { read_verilog ${DesignName}.vm } if {[file exists ${DesignName}.xdc]} { read_xdc ${DesignName}.xdc } if {[file exists ${DesignName}_floorplan.xdc]} { read_xdc ${DesignName}_floorplan.xdc } set TopModule [find_top] set_property top ${TopModule} [current_fileset] }
read_xdc pin_loc.xdc
################################################# ### RUN DESIGN ### ################################################# #run link_design link_design if {[file exists "clock_groups.tcl"]} {source clock_groups.tcl} #Evaluate options and run opt_design eval opt_design $opt_design_flags
### FOR INCREMENTAL FLOW ### puts"Flow is ${Flow}" if {${Flow} == "Incremental"} { #Use DCP from previous P&R run for Incremental Flow if {[file exists "${DesignName}.dcp"]} { puts"Using ${DesignName}.dcp for Incremental Place and Route" read_checkpoint -incremental ${DesignName}.dcp report_incremental_reuse } else { puts"${DesignName}.dcp does not exist. Running Place and Route" } } #Evaluate options and run place_design eval place_design $place_design_flags write_checkpoint -force post_place.dcp #Evaluate options and run route_design eval route_design $route_design_flags #set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design] write_checkpoint -force ${DesignName}.dcp
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