always_ff @(posedge clk orposedge rst) begin if (rst) begin led <= 4'b0000; end elsebegin if (!dirct) begin if (led == 0) led <= 4'b0001; else led <= led << 1; end elsebegin if (led == 0) led <= 4'b1000; else led <= led >> 1; end end end
always_combbegin case (sw) 2'b01: dirct = 1'b0; 2'b10: dirct = 1'b1; default: dirct = 1'b0; endcase end
Following is like the last project : Out-of-Context XDC files setting -> Create and Package New IP -> Package your current project -> edit Ports and Interfaces -> Package IP
Close blinky_module Project
3、Create top Project
Project Name : “top” -> Next -> Choose “Boards / ZedBoard Zynq Evaluation and Development Kit” -> Finish
Include divide IP, Path :”Your path”divider_moduledivider_module.srcs
Include blinky IP, Path :”Your path”blinky_moduleblinky_module.srcs
Create Block Design
Create Port and connect module
Run Synthesis -> Run Implementation -> Open Implementation
近期评论