pwm modelsim 仿真模擬

module PWM(
  input       iClk,     
  input       iRst_n,
  output reg  oPWM        //PWM signal out
);

reg [3:0]     rPwmCounter = 0;
parameter     rDutyCycle  = 11'h7ff;


[email protected](negedge iClk or negedge iRst_n) begin
  if(!iRst_n) rPwmCounter <= 10'd0;
    else             
      begin
      if ( rPwmCounter < 7 ) //50%
        oPWM <= 1;
      else
        oPWM <= 0;
      rPwmCounter <= rPwmCounter+1;
    end
end


endmodule

`timescale 1ns/100ps

module PWM_tb;

  reg       iclk50M;     
  reg       irst_n;
  wire      opwm;        //PWM signal out


parameter PERIOD50M = 20; 
PWM pwm1(
           .iClk(iclk50M),     
           .iRst_n(irst_n),
           .oPWM(opwm)        //PWM signal out
);


initial begin
  #0 iclk50M = 1'b0;
     irst_n  = 1'b0;
  #5 irst_n  = 1'b1;
end

// 50MHz
always #(PERIOD50M/2) iclk50M = ~iclk50M;

endmodule